000			00485nam a2200181Ia 4500
008			140908s9999 xx 000 0 und d
020			_a9788131501955
040			_aNISER LIBRARY
041			_aEnglish
082			_a621.38 _bUYE-C
100			_aVyemura, J P
245			_aChip design for submicron VLSI:cmos layout and simulation _cJohn P Uyemura
260			_aAustralia _bCengage learning _c2006
300			_axvi, 411p.
650			_aCHIP DESIGN
650			_aVLSI
942			_cBK
999			_c7926 _d7926